Laterally diffused metal oxide semiconductor (LDMOS) device mainly features that there is a relatively long lightly doped drift region between the channel region and the drain region, the drift region has the same doping type as that of the drain, thus it can play a role of balancing the breakdown voltage.
In super junction LDMOS, the lightly doped drift region of the conventional LDMOS is substituted by N-column regions and P-column regions which are arranged alternatively. Theoretically, due to the charge compensation between P/N column regions, a higher breakdown voltage of the super junction LDMOS can be obtained, and the N-column region can obtain a lower on-resistance due to its higher doping concentration, such that the super junction LDMOS can obtain a good balance between higher breakdown voltage and lower on-resistance.
The super junction LDMOS is substantially equivalent to implanting a PN junction into the drift region. When the device is working at the maximum breakdown voltage, the drift region can be completely depleted as much as possible. Accordingly, in addition to N-column regions withstand the main voltage, the depletion layer at the PN junction interface also withstands part of the voltage, therefore the super junction LDMOS can withstand higher breakdown voltage comparing to the conventional LDMOS.
In order to withstand an even higher breakdown voltage for the device, a width between P/N columns can be reduced, and a depth of the P/N columns can be increased. However, column region with too much depth will inevitably be accompanied by high-energy ion implantation, which may cause interior damage to the device. In addition, the high-energy ion implantation may result in an uneven distribution of the interior impurities of the column region, thus reducing the actual anti-breakdown capability.